[1]易璐茗,祁楠,杨骁.高线性度大摆幅56 Gbit/s PAM4驱动电路设计[J].集美大学学报(自然科学版),2022,27(5):474-480.
 YI Luming,QI Nan,YANG Xiao.Design of 56 Gbit/s PAM4 Driving Circuit with High Linearity and Large Swing[J].Journal of Jimei University,2022,27(5):474-480.
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高线性度大摆幅56 Gbit/s PAM4驱动电路设计()
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《集美大学学报(自然科学版)》[ISSN:1007-7405/CN:35-1186/N]

卷:
第27卷
期数:
2022年第5期
页码:
474-480
栏目:
数理科学与信息工程
出版日期:
2022-09-28

文章信息/Info

Title:
Design of 56 Gbit/s PAM4 Driving Circuit with High Linearity and Large Swing
作者:
易璐茗12祁楠23杨骁1
(1.华侨大学信息科学与工程学院,福建 厦门 361021;2.中国科学院半导体研究所,北京 100083;3.中国科学院大学,北京 100049)
Author(s):
YI Luming12QI Nan23YANG Xiao1
(1.College of Information Science and Engineering,Huaqiao University,Xiamen 361021,China;2.Institute of Semiconductors,Chinese Academy of Science,Beijing 100083,China;3.University of Chinese Academy of Science,Beijing 100049,China)
关键词:
四电平脉冲调制去加重高线性度大摆幅电压模驱动电路
Keywords:
4-level pulse amplitude modulationde-emphasishigh linearitylarge swingvoltage mode driver
文献标志码:
A
摘要:
面向高速串行接口发送端应用,设计了具有二阶去加重均衡功能的高线性度大摆幅四电平脉冲幅度调制(4 pulse amplitude modulation,PAM4)电压模驱动电路。采用查表的方式对信道损耗进行灵活补偿;在输出端并联两个电阻解决传统电压模驱动电路设计中线性度较低的问题;采用反相器堆叠的推挽式结构实现了高输出摆幅;提出一种新型电平转移电路,解决了连续0或1数字码产生的直流电平漂移问题。仿真结果表明,驱动电路的电平失配率为97.9%,去加重均衡实现6.6 dB、13 dB和19.6 dB三种去加重级数,差分输出摆幅为2 V,功耗效率为2.3 mW/(Gbit/s)。
Abstract:
For high-speed serial interface transmitter applications,this paper designs a high linearity and large swing four-level pulse amplitude modulation(PAM4) voltage mode driving circuit with second-order de-emphasis equalization.The circuit employs a lookup table (LUT)based approach to flexibly compensate the channel loss.By embedding an additional two resistors into the output terminal,the low linearity of traditional voltage mode driving circuit can be solved.Output driver circuit adopts a push-pull structure based on inverter stacking to achieve high output swing,in which a new type of level shift circuit is adopted to reduce the problem of DC level drift caused by continuous 0 or 1 digital code.Measurement results show that the ratio of level mismatch(RLM)is 97.9%,de-emphasis equalization realizes three de-emphasis levels of 6.6 dB,13 dB and 19.6 dB,the circuit exhibits 2 V differential output swing and 2.3 mW/(Gbit/s)power consumption efficiency.
更新日期/Last Update: 2022-11-18